Description
Data Active Time Before Clock Pulse (Data Set-Up Time) Data Active Time After Clock Pulse (Data Hold Time) Clock Pulse Width Time Between Clock Activation and Strobe Strobe Pulse Width
Symbol tsu(D) th(D) tw(CH) tsu(C) tw(STH)
Time (ns) 25 25 50 100 50
NOTE: Timing is representative of a 10 MHz c
Features
- 3.3 V to 5 V logic supply range To 10 MHz data input rate 30 V minimum output breakdown Darlington current-sink outputs Low-power CMOS logic and latches Schmitt trigger inputs for improved noise immunity.
A6833 Datasheet
