Datasheet4U Logo Datasheet4U.com

AS7C33128FT18B - 3.3V 128K x 18 Flow Through Synchronous SRAM

General Description

The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words × 18 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns.

Three chip enable (CE) inputs permit easy memory expansion.

Key Features

  • Organization: 131,072 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Economical 100-pin TQFP package Individual byte write and Global write Multiple chip enables for easy expansion.
  • 3.3V core power supply 2.5V or 3.3V I/O operation with separate V.

📥 Download Datasheet

Datasheet Details

Part number AS7C33128FT18B
Manufacturer Alliance Semiconductor Corporation
File Size 444.83 KB
Description 3.3V 128K x 18 Flow Through Synchronous SRAM
Datasheet download datasheet AS7C33128FT18B Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
AS7C33128NTD32A 3.3V 128K X 32/36 SRAM Alliance Semiconductor
AS7C33128NTD36A 3.3V 128K X 32/36 SRAM Alliance Semiconductor
AS7C33256NTD16A 3.3V 256K X 16/18 SRAM Alliance Semiconductor
AS7C33256NTD18A 3.3V 256K X 16/18 SRAM Alliance Semiconductor
AS7C31024 5V/3.3V 128K x 8 CMOS SRAM Alliance Semiconductor

Other Datasheets by Alliance Semiconductor Corporation

Part Number Description
AS7C33128FT32B (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
AS7C33128FT36B (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
AS7C33128NTD18B 3.3V 128Kx18 Pipelined SRAM
AS7C33128NTD32B (AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM
AS7C33128NTD36B (AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
December 2004 ® AS7C33128FT18B 3.3V 128K × 18 Flow Through Synchronous SRAM Features • • • • • • • • Organization: 131,072 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Economical 100-pin TQFP package Individual byte write and Global write Multiple chip enables for easy expansion • • • • • 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs www.DataSheet4U.