AS7C33128FT18B Datasheet | Alliance Semiconductor Corporation

Features - - - - - - - - Organization: 131,072 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Economical 100-pin TQFP package Individual byte write and Global write Multiple chip enables for easy expansion - - - - - 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby mon data inputs and data outputs .. Logic block diagram CLK ADV ADSC ADSP A[16:0] CLK CS CLR Burst logic 2 2 Q D CS Address register CLK 128K × 18 Memory array 17 18 18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb Byte Write registers CLK D DQa Q Byte Write registers CLK D Enable register CE CLK Output Buffers Input registers Power down D Enable Q delay register CLK OE 18 DQ [a,b] Selection guide - 65 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 7.5 6.5 250 120 30 -75 8.5 7.5 225 100 30 -80 10 8.0 200 90 30 -10 12 10.0 175 90 30 Units ns ns m A m A m...