AS7C33256FT18B Datasheet | Alliance Semiconductor Corporation

December 2004 ® 3.3V 256K × 18 Flow Through Synchronous SRAM Features - - - - - - - Organization: 262,144 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Availalbe in 100-pin TQFP package Individual byte write and Global write - - - - - - Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby mon data inputs and data outputs .. Logic block diagram CLK ADV ADSC ADSP A[17:0] CLK CS CLR Burst logic 2 2 Q D CS Address register CLK 256K × 18 Memory array 18 18 18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb Byte Write registers CLK D DQa Q Byte Write registers CLK D Enable register CE CLK Output Buffers Input registers Power...