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AS7C33256FT18B - 3.3V 256K x 18 Flow Through Synchronous SRAM

General Description

The AS7C33256FT18B is a high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized as 262,144 words × 18 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns.

Three chip enable (CE) inputs permit easy memory expansion.

Key Features

  • Organization: 262,144 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Availalbe in 100-pin TQFP package Individual byte write and Global write.
  • Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate.

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Datasheet Details

Part number AS7C33256FT18B
Manufacturer Alliance Semiconductor Corporation
File Size 447.04 KB
Description 3.3V 256K x 18 Flow Through Synchronous SRAM
Datasheet download datasheet AS7C33256FT18B Datasheet

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AS7C33256FT32A (AS7C33256FT32A / AS7C33256FT36A) 3.3V 256K x 32/36 Flow-through synchronous SRAM
AS7C33256FT36A (AS7C33256FT32A / AS7C33256FT36A) 3.3V 256K x 32/36 Flow-through synchronous SRAM
AS7C33256NTD18B 3.3V 256K x 8 Pipelined SRAM
AS7C33256NTD32A (AS7C33256NTD32A / AS7C33256NTD36A) 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM
AS7C33256NTD36A (AS7C33256NTD32A / AS7C33256NTD36A) 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM
AS7C33256NTF18B 3.3V 256K x 18 Flowthrough Synchronous SRAM
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AS7C33256NTF36A (AS7C33256NTF32A / AS7C33256NTF36A) 3.3V 256K x 2/36 Flowthrough Synchronous SRAM
AS7C33256PFD18B 3.3V 256K x 18 pipeline burst synchronous SRAM
AS7C33256PFD32A (AS7C33256PFD32A / AS7C33256PFD36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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December 2004 ® AS7C33256FT18B 3.3V 256K × 18 Flow Through Synchronous SRAM Features • • • • • • • Organization: 262,144 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Availalbe in 100-pin TQFP package Individual byte write and Global write • • • • • • Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs www.DataSheet4U.