AS7C33256NTD32A Datasheet | Alliance Semiconductor Corporation

November 2004 ® AS7C33256NTD32A AS7C33256NTD36A 3.3V 256K×32/36 Pipelined burst Synchronous SRAM with NTDTM Features - Organization: 262,144 words × 32 or 36 bits - NTD™architecture for efficient bus operation - Fast clock speeds to 166 MHz - Fast clock to data access: 3.5/4.0 ns - Fast OE access time: 3.5/4.0 ns - Fully synchronous operation - mon data inputs and data outputs .. - Asynchronous output enable control - Available in 100-pin TQFP - Byte write enables - Clock enable for operation hold - Multiple chip enables for easy expansion - 3.3 core power supply - 2.5V or 3.3V I/O operation with separate VDDQ - Self-timed write cycles - Interleaved or linear burst modes - Snooze mode for standby operation Logic Block Diagram A[17:0] 18 D Address register Burst logic CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ 36/32 Write delay addr. registers Q 18 Control logic Write...