AS7C33256NTF18B - 3.3V 256K x 18 Flowthrough Synchronous SRAM
Alliance Semiconductor Corporation
General Description
The AS7C33256NTF18B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 18 bits and incorporates a LATE Write.
Key Features
Organization: 262,144 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package.
Byte write enables Clock enable for operation hold Multiple chip e.
Full PDF Text Transcription for AS7C33256NTF18B (Reference)
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April 2005 ® AS7C33256NTF18B 3.3V 256K x 18 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • Organization: 262,144 words × 18 bits NTD™ architecture for e...
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• • • • Organization: 262,144 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • • Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation www.DataSheet4U.
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AS7C33256NTF18B Datasheet
