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AS7C3364FT32B - (AS7C3364FT32B / AS7C3364FT36B) 3.3V 64K x 32/36 Flow Through Synchronous SRAM

General Description

The AS7C3364FT32B/36B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as 65,536 words × 32 or 36 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns.

Key Features

  • Organization: 65,536 words × 32 or 36 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and Global write.
  • Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with s.

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Datasheet Details

Part number AS7C3364FT32B
Manufacturer Alliance Semiconductor Corporation
File Size 463.27 KB
Description (AS7C3364FT32B / AS7C3364FT36B) 3.3V 64K x 32/36 Flow Through Synchronous SRAM
Datasheet download datasheet AS7C3364FT32B Datasheet

Full PDF Text Transcription for AS7C3364FT32B (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for AS7C3364FT32B. For precise diagrams, and layout, please refer to the original PDF.

February 2005 ® AS7C3364FT32B AS7C3364FT36B 3.3V 64K × 32/36 Flow Through Synchronous SRAM Features • • • • • • • Organization: 65,536 words × 32 or 36 bits Fast clock to...

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• • • • • • • Organization: 65,536 words × 32 or 36 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and Global write • • • • • • Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs www.DataSheet4U.

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