AS7C3364NTF32B Datasheet | Alliance Semiconductor Corporation

Features - Organization: 65,536 words × 32 or 36 bits - NTD™architecture for efficient bus operation - Fast clock to data access: 7.5/8.0/10.0 ns - Fast OE access time: 3.5/4.0 ns - Fully synchronous operation - Flow-through mode - Asynchronous output enable control - Available in 100-pin TQFP package .. - Byte write enables - Clock enable for operation hold - - - - - - Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic block diagram A[15:0] 16 D Address register Burst logic CLK CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ Q 16 Write delay addr. registers Control logic Write Buffer 64K x 32/36 SRAM Array DQ[a,b,c,d] 32/36 Data Q Input Register 32/36 32/36 32/36 32/36 CLK CEN OE Output Buffer 32/36 OE DQ[a,b,c,d] Selection...