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AS4C32M16SM - 512M (32M x 16) bit Synchronous DRAM

Key Features

  • PC133-compliant.
  • Configurations.
  • 32 Meg x 16 (8 Meg x 16 x 4 banks).
  • Fully synchronous; all signals registered on positive edge of system clock.
  • Internal, pipelined operation; column address can be changed every clock cycle.
  • Internal banks for hiding row access/precharge.
  • Programmable burst lengths: 1, 2, 4, 8, or full page.
  • Auto precharge, includes concurrent auto precharge and auto refresh modes.
  • Self refresh mode.
  • Auto refresh.
  • 64m.

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Datasheet Details

Part number AS4C32M16SM
Manufacturer Alliance Semiconductor
File Size 2.65 MB
Description 512M (32M x 16) bit Synchronous DRAM
Datasheet download datasheet AS4C32M16SM Datasheet

Full PDF Text Transcription for AS4C32M16SM (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for AS4C32M16SM. For precise diagrams, and layout, please refer to the original PDF.

AS4C32M16SM 512M (32M x 16) bit Synchronous DRAM (SDRAM) Confidential Preliminary (Rev. 1.0, July /2014) Revision History AS4C32M16SM Revision Details Rev 1.0 Preliminary...

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014) Revision History AS4C32M16SM Revision Details Rev 1.0 Preliminary datasheet Date July 2014 Confidential 1|P a g e Rev1.0, July 2014 AS4C32M16SM Confidential 512M (32M x 16) bit Synchronous DRAM (SDRAM) Preliminary (Rev. 1.