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AS4C8M16S - 128M - 8M x 16 bit Synchronous DRAM

General Description

Table 3.

Symbol CLK Type Input Description Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

Key Features

  • Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 2M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function.
  • Auto Refresh and Self Refresh.
  • 4096 refresh cycles/64ms.
  • CKE power down mode.
  • Single +3.3V  0.3V power supply.
  • Interface: LVTTL.
  • Operating temperature range - Co.

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Datasheet Details

Part number AS4C8M16S
Manufacturer Alliance Semiconductor
File Size 1.03 MB
Description 128M - 8M x 16 bit Synchronous DRAM
Datasheet download datasheet AS4C8M16S Datasheet

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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AS4C8M16S 128M - 8M x 16 bit Synchronous DRAM (SDRAM) Confidential Features Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 2M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function  Auto Refresh and Self Refresh  4096 refresh cycles/64ms  CKE power down mode  Single +3.3V  0.3V power supply  Interface: LVTTL  Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C) - Automotive A2 (-40 ~ 105°C) 54-pin 400 mil plastic TSOP II package   54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package All parts ROHS Compliant       (Rev. 2, Feb.