Datasheet4U Logo Datasheet4U.com

AS8C401825 - 3.3V Synchronous SRAMs

This page provides the datasheet information for the AS8C401825, a member of the AS8C403625 3.3V Synchronous SRAMs family.

Description

TheAS8C403625/1825 are high-speed SRAMs organized as 128K x 36/256K x 18.

The AS8C403625/1825 SRAMs contain write, data, address and control registers.

There are no registers in the data output path (flow-through architecture).

Features

  •   AS8C403625 AS8C401825.

📥 Download Datasheet

Datasheet preview – AS8C401825

Datasheet Details

Part number AS8C401825
Manufacturer Alliance Semiconductor
File Size 885.30 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet AS8C401825 Datasheet
Additional preview pages of the AS8C401825 datasheet.

📁 Similar Datasheet

  • AS8002 - Solar Photovoltaic Inverter Measurement IC (austriamicrosystems AG)
  • AS8002 - SMTO-8 CASCADABLE AMPLIFIER (TELEDYNE)
  • AS8118 - Single Phase Instantaneous Energy Metering IC (austriamicrosystems AG)
  • AS8168 - Single Phase Average Energy Metering IC (austriamicrosystems AG)
  • AS81F641642C - 1M x 16 Bit x 4 Banks SYNCHRONOUS DRAM (ASMIC)
  • AS8201 - TTP/C-C1 Communications Controller (austriamicrosystems AG)
  • AS8202 - TTP/C-C2 Communication Controller (austriamicrosystems AG)
  • AS8202B - TTP-C2NF Communication Controller (ams)
  • AS8202NF - TTP-C2NF Communication Controller (austriamicrosystems AG)
  • AS8218 - Highly Integrated Single Phase 2 Current Energy Metering Integrated Circuits (austriamicrosystems AG)
Other Datasheets by Alliance Semiconductor

Full PDF Text Transcription

Click to expand full text
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆   AS8C403625 AS8C401825 Description TheAS8C403625/1825 are high-speed SRAMs organized as 128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the AS8C403625/1825 can provide four cycles of data for a single address presented to the SRAM.
Published: |