AS8C403625 Description
TheAS8C403625/1825 are high-speed SRAMs organized as 128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture).
AS8C403625 Key Features
- 7.5ns up to 117MHz clock frequency
- LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write ena
- Boundary Scan JTAG Interface (IEEE 1149.1 pliant) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP)