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AS8C801800 - 3.3V Synchronous SRAMs

This page provides the datasheet information for the AS8C801800, a member of the AS8C803600 3.3V Synchronous SRAMs family.

Description

256K x 36 / 512K x 18.

The SRAMs contain write, data, address and control registers.

Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.

Features

  • 256K x 36, 512K x 18 memory configurations Supports high system speed:.
  • 150MHz 3.8ns clock access time.
  • LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP).

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Datasheet Details

Part number AS8C801800
Manufacturer Alliance Semiconductor
File Size 8.09 MB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet AS8C801800 Datasheet
Additional preview pages of the AS8C801800 datasheet.

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Full PDF Text Transcription

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256K X 36, 512K X 18 3.3V Synchronous SRAMs AS8C803600 3.3V I/O, Burst Counter AS8C801800 Pipelined Outputs, Single Cycle Deselect Features 256K x 36, 512K x 18 memory configurations Supports high system speed: – 150MHz 3.8ns clock access time ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP) Description The 256K x 36 / 512K x 18. The SRAMs contain write, data, address and control registers.
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