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AS8C803601 - 3.3V Synchronous ZBT SRAMs

Description

The AS8C803601/801801 SRAM utilize IDT's latest high-performance The AS8C803601/801801 are3.3V high-speed 9,437,184 bit CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100(9 Megabit) synchronous SRAMS.

They are designed to eliminate dead bus pin thin plastic quad flatpack (TQFP) .

Features

  • Pin.

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Datasheet preview – AS8C803601

Datasheet Details

Part number AS8C803601
Manufacturer Alliance Semiconductor
File Size 1.56 MB
Description 3.3V Synchronous ZBT SRAMs
Datasheet download datasheet AS8C803601 Datasheet
Additional preview pages of the AS8C803601 datasheet.

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Full PDF Text Transcription

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256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs ◆ AS8C803601 AS8C801801 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. 256K x 36, 512K x 18 memory configurations ◆ The AS8C803601/801801 contain data I/O, address and control signal Supports high performance system speed - 150MHz registers. Output enable is the only asynchronous signal and can be (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles used to disable the outputsat any given time.
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