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EP1C4 - FPGA

This page provides the datasheet information for the EP1C4, a member of the EP1C3 FPGA family.

Datasheet Summary

Description

Logic Array Blocks6 Logic Elements 9 MultiTrack Interconnect 17 Embedded Memory23 Global Clock Network & Phase-Locked Loops34 I/O Structure 44 Power Sequencing & Hot Socketing 60 IEEE Std.

Features

  • The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path.

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Datasheet preview – EP1C4

Datasheet Details

Part number EP1C4
Manufacturer Altera
File Size 1.08 MB
Description FPGA
Datasheet download datasheet EP1C4 Datasheet
Additional preview pages of the EP1C4 datasheet.

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Full PDF Text Transcription

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April 2003, ver. 1.2 ® Cyclone FPGA Family Data Sheet Introduction Preliminary Information Features... The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices.
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