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May 1995, ver. 1
Features
EP220 & EP224
® Classic EPLDs
Data Sheet
s High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 macrocells – Combinatorial speeds as low as 7.5 ns – Counter frequencies of up to 100 MHz – Pipelined data rates of up to 115 MHz – Maximum 5.5-ns Clock-to-output time; minimum 4.
EP220 Datasheet
