AD6652 Datasheet | Analog Devices

FEATURES SNR = 90 d B in 150 k Hz bandwidth (to Nyquist @ 61.44 MSPS) Worst harmonic = 83 d Bc (to Nyquist @ 61.44 MSPS) Integrated dual-channel ADC: Sample rates up to 65 MSPS IF sampling frequencies to 200 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range (1 V to 2 V p-p) Differential analog inputs ADC clock duty cycle stabilizer 85 d B channel isolation/crosstalk Integrated wideband digital downconverter (DDC): Crossbar switched DDC inputs Digital resampling for noninteger decimation Programmable decimating FIR filters Flexible control for multicarrier and phased array Dual AGC stages for output level control Dual 16-bit parallel or 8-bit link output ports User-configurable built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONS munications Diversity radio systems Multimode digital receivers: GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE, IS95, IS136, CDMA2000, IMT-2000 I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Instrumentation and test equipment FUNCTIONAL BLOCK DIAGRAM DUAL-CHANNEL 12-BIT A/D FRONT END VINA+ SHA VINA- REFTA REFBA VREF SENSE REFTB REFBB VINB+ SHA VINB- ADC CHANNEL B 12 VREF WIDEBAND DIGITAL DOWNCONVERTER (DDC) RCIC2 CIC5 RESAMPLER NCO RCIC2 CIC5 RESAMPLER NCO RCIC2 CIC5 RESAMPLER NCO RCIC2 CIC5 RESAMPLER NCO RAM COEF. FILTER CHANNEL 3 RAM COEF. FILTER CHANNEL 0 RAM COEF. FILTER CHANNEL 1 RAM COEF. FILTER CHANNEL 2 TO OUTPUT PORTS RCF OUTPUTS CHANNELS 0, 1, 2, 3 TO OUTPUT PORTS PORT A 8-BIT DSP LINK OR 16-BIT PARALLEL OUTPUT CONTROL OUTPUT MUX CIRCUITRY PORT B AGC B- TO OUTPUT PORTS RCF OUTPUTS CHANNELS 0, 1, 2, 3 8-BIT DSP LINK OR 16-BIT PARALLEL OUTPUT 12 ADC CHANNEL A / CHANNEL A OTRA LIA LIA PSEUDO RANDOM NOISE SEQUENCE LIB LIB OTRB CHANNEL B INPUT MATRIX AGC A- TO OUTPUT PORTS / - DATA INTERLEAVING AND INTERPOLATING HB FILTER CONTROL PDWN SHRDREF MODE SELECT ACLK DUTYEN CLOCK DUTY CYCLE STABILIZER...