AD6653 - IF Diversity Receiver

4 Specifications 5 ADC DC Specifications 5 ADC AC Specifications 6 Digital Specifications 7 Switching Specifications 9 Timing Specifications 10 Absolute Maximum Ratings 13 Thermal Characteristics 13 ESD Caution 13 Pin Configurations and Function Descriptions 14 Equivalent Circuits 18 Typica

• SNR = 70.8 dBc (71.8 dBFS) in a 32.7 MHz BW at 70 MHz @ 150 MSPS SFDR = 83 dBc to 70 MHz @ 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply Integer 1-to-8 input clock divider Integrated dual-channel ADC Sample rates up to 150 MSPS IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk.