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AD9528 - JESD204B/JESD204C Clock Generator

General Description

The AD9528 is a two-stage PLL with an integrated JESD204B/ JESD204C SYSREF generator for multiple device synchronization.

The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock.

Key Features

  • 14 outputs configurable for HSTL or LVDS.
  • Maximum output frequency.
  • 6 outputs up to 1.25 GHz.
  • 8 outputs up to 1 GHz.
  • Dependent on the voltage controlled crystal oscillator (VCXO) frequency accuracy (start-up frequency accuracy:.

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Full PDF Text Transcription for AD9528 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for AD9528. For precise diagrams, and layout, please refer to the original PDF.

Data Sheet AD9528 JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs FEATURES ► 14 outputs configurable for HSTL or LVDS ► Maximum output frequency ► 6 outputs u...

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configurable for HSTL or LVDS ► Maximum output frequency ► 6 outputs up to 1.25 GHz ► 8 outputs up to 1 GHz ► Dependent on the voltage controlled crystal oscillator (VCXO) frequency accuracy (start-up frequency accuracy: <±100 ppm) ► Dedicated 8-bit dividers on each output ► Coarse delay: 63 steps at 1/2 the period of the RF VCO divider output frequency with no jitter impact ► Fine delay: 15 steps of 31 ps resolution ► Typical output to output skew: 20 ps ► Duty cycle correction for odd divider settings ► Output 12 and Output 13, VCXO output at power-up ► Absolute output jitter: <160 fs at 122.

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