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AD9520-5 - 12 LVPECL/24 CMOS Output Clock Generator

Features

  • Low phase noise, phase-locked loop (PLL) Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/ manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog.

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Datasheet Details

Part number AD9520-5
Manufacturer Analog Devices
File Size 1.17 MB
Description 12 LVPECL/24 CMOS Output Clock Generator
Datasheet download datasheet AD9520-5 Datasheet
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Other Datasheets by Analog Devices
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  • AD9522-2 - 12 LVDS/24 CMOS Output Clock Generator

Full PDF Text Transcription

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Data Sheet 12 LVPECL/24 CMOS Output Clock Generator AD9520-5 FEATURES Low phase noise, phase-locked loop (PLL) Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/ manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.
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