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AD9520-1 - 12 LVPECL/24 CMOS Output Clock Generator

Key Features

  • Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.27 GHz to 2.65 GHz Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automat.

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Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO AD9520-1 FEATURES Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.27 GHz...

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w phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.27 GHz to 2.65 GHz Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.

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