Datasheet Details
| Part number | AD9531 |
|---|---|
| Manufacturer | Analog Devices |
| File Size | 1.08 MB |
| Description | 3-Channel Clock Generator |
| Datasheet |
 AD9531 Datasheet
|
|
|
General Description
The AD9531 provides a multioutput clock generator function and three on-chip phase-locked loop (PLL) cores with SPI programmable output frequencies and formats.
PLL1 provides two reference inputs and 10 outputs and includes four user selectable loop configurations.
Key Features
- 3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3) Jitter performance: 0.462 ps rms typical PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth Loss of reference and lock detection for each PLL Pin-configurable common frequency translations Automatic synchronization of all outputs on power-up Manual output synchronization capability Package available in an 88-lead LFCSP PLL1 details Fractional-N/integer-N modes Optional external VCXO Fixed delay mode for constant static phase offset 2 refer.