FEATURES
3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3) Jitter performance: 0.462 ps rms typical PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth Loss of reference and lock detection for each PLL Pin-configurable common frequency translations Automatic synchronization of all outputs on power-up Manual output synchronization capability Package available in an 88-lead LFCSP PLL1 details Fractional-N/integer-N modes Optional external VCXO Fixed delay mode for constant static phase offset 2 reference clock inputs Input format: differential/single-ended Frequency range: 9.5 MHz to 260 MHz Reference switching: manual/automatic 10 ultralow jitter HSTL/CMOS outputs up to 400 MHz PLL2 details Integer-N mode (1 reference clock input) Input format: differential/single-ended/crystal1 Frequency range: 9.5 MHz to 250 MHz 12 HSTL/CMOS outputs up to 400 MHz PLL3 details Integer-N mode (1 reference clock input) Frequency range: 9.5 MHz to 100 MHz Input format: differential/crystal (supports...
Analog Devices
