AD9547 - Dual/Quad Input Network Clock Generator/Synchronizer

Analog Devices

General Description

The AD9547 provides synchronization for many systems, including synchronous optical networks (SONET/SDH).

The AD9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references.

Key Features

Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent singleended inputs Input reference frequencies from 1 kHz to 750 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 30-bit programmable input refe.

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AD9547 dual/quad input network clock generator/synchronizer by Analog Devices - Datasheet Preview

Datasheet Details

Part number	AD9547
Manufacturer	Analog Devices
File Size	1.55 MB
Description	Dual/Quad Input Network Clock Generator/Synchronizer
Datasheet	AD9547 Datasheet

Full PDF Text Transcription for AD9547 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for AD9547. For precise diagrams, and layout, please refer to the original PDF.

Data Sheet Dual/Quad Input Network Clock Generator/Synchronizer AD9547 FEATURES Supports Stratum 2 stability in holdover mode Supports reference switchover with phase bui...

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tability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent singleended inputs Input reference frequencies from 1 kHz to 750 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 30-bit programmable input reference divider 2 pairs of clock output pins, with each pair configurable as a single differential LVDS/LVPECL output or as 2 singleended CMOS outputs O

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