AD9577 - Clock Generator

Features

Fully integrated dual PLL/VCO cores 1 integer-N and 1 fractional-N PLL Continuous frequency coverage from 11.2 MHz to 200 MHz Most frequencies from 200 MHz to 637.5 MHz available PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical PLL2 phase jitter (12 kHz to 20 MHz) Integer-N mode: 470 fs rms typical Fractional-N mode: 660 fs rms typical Input crystal or reference clock frequency Optional reference frequency divide-by-2 I2C programmable output frequencies Up to 4 LVDS/LVPECL or up to 8 LVC.

Analog Devices

Datasheet Details

Part number	AD9577
Manufacturer	Analog Devices
File Size	785.28 KB
Description	Clock Generator
Datasheet	AD9577 Datasheet
Additional preview pages of the AD9577 datasheet.

📁 Similar Datasheet

AD9256 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
AD9256H - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
AD92580 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
AD92580C - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
AD9700 - Video Dispaly D/A Converter (ETC)

Other Datasheets by Analog Devices

AD9571 - Ethernet Clock Generator
AD9572 - Fiber Channel/Ethernet Clock Generator IC
AD9573 - PCI-Express Clock Generator IC
AD9574 - Ethernet/Gigabit Ethernet Clock Generator
AD9575 - Network Clock Generator
AD9576 - Asynchronous Clock Generator
AD9578 - Dual PLL Precision Synthesizer
AD9500 - Digitally Programmable Delay Generator

Full PDF Text Transcription

Click to expand full text

Data Sheet Clock Generator with Dual PLLs, Spread Spectrum, and Margining AD9577 FEATURES Fully integrated dual PLL/VCO cores 1 integer-N and 1 fractional-N PLL Continuous frequency coverage from 11.2 MHz to 200 MHz Most frequencies from 200 MHz to 637.5 MHz available PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical PLL2 phase jitter (12 kHz to 20 MHz) Integer-N mode: 470 fs rms typical Fractional-N mode: 660 fs rms typical Input crystal or reference clock frequency Optional reference frequency divide-by-2 I2C programmable output frequencies Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks 1 CMOS buffered reference clock output Spread spectrum: downspread [0, −0.

Published: Jan 4, 2017 |