Description
43 Applications 46 Design Guidelines 46 Evaluation Board 47 Power Supplies 47 Input Signals 47 Output Signals 47 Default Operation and Jumper Selection Settings 48 Alternative Clock Configurations 48 Alternative Analog Input Drive Configuration 49 Schematics 50 Evaluation Board Layouts 60 Bill
Features
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SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS SFDR = 81 dBc to 70 MHz at 150 MSPS Low power: 825 mW at 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply Integer 1 to 8 input clock divider Intermediate frequency (IF) sampling frequencies up to 450 MHz Internal analog-to-digital converter (ADC) voltage reference Integrated ADC sample-and-hold inputs Flexible analog input: 1 V p-p to 2 V p-p range Differential analog inputs with 650.
AD9600 Datasheet
