AD9684 Datasheet | Analog Devices

Data Sheet AD9684 14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter Features - Parallel LVDS (DDR) outputs - 1.1 W total power per channel at 500 MSPS (default settings) - SFDR = 85 d BFS at 170 MHz f IN (500 MSPS) - SNR = 68.6 d BFS at 170 MHz f IN (500 MSPS) - ENOB = 10.9 bits at 170 MHz f IN - DNL = ±0.5 LSB - INL = ±2.5 LSB - Noise density = - 153 d BFS/Hz at 500 MSPS - 1.25 V, 2.50 V, and 3.3 V supply operation - No missing codes - Internal analog-to-digital converter (ADC) voltage reference - Flexible input range and termination impedance - 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) - 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential - SYNC± input allows multichip synchronization - DDR LVDS (ANSI-644 levels) outputs - 2 GHz usable analog input full power bandwidth - >96 d B channel isolation/crosstalk - Amplitude detect bits for efficient AGC implementation FUNCTIONAL BLOCK DIAGRAM - Two integrated wideband digital processors per channel - 12-bit numerically controlled oscillator (NCO) - 3 cascaded half-band filters - Differential clock inputs - Serial port control - Integer clock divide by 2, 4, or...