AD9695
FEATURES
JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps
1.6 W total power at 1300 MSPS 800 m W per ADC channel
SNR = 65.6 d BFS at 172 MHz (1.59 V p-p input range) SFDR = 78 d BFS at 172.3 MHz (1.59 V p-p input range) Noise density
- 153.9 d BFS/Hz (1.59 V p-p input range)
- 155.6 d BFS/Hz (2.04 V p-p input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical) 2 GHz usable analog input full power bandwidth >95 d B channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity
APPLICATIONS munications Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, WCDMA, GSM,...
