AD9697
FEATURES
JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps
Total power dissipation: 1.00 W at 1300 MSPS SNR: 65.6 d BFS at 172.3 MHz (1.59 V p-p analog input full scale) SFDR: 78 d BFS at 172.3 MHz (1.59 V p-p analog input full scale) Noise density
- 153.9 d BFS/Hz (1.59 V p-p analog input full scale)
- 155.6 d BFS/Hz (2.04 V p-p analog input full scale) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible differential input voltage range 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical) 2 GHz usable analog input full power bandwidth Amplitude detect bits for efficient AGC implementation 4 integrated digital downconverters 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity
APPLICATIONS
Co...
