AD9868 Datasheet | Analog Devices

FEATURES Low cost 3.3 V CMOS Mx FE for broadband modems 10-bit DAC converter 2×/4× interpolation filter 200 MSPS DAC update rate Integrated 17 d Bm line driver with 19.5 d B gain control 10-bit, 80 MSPS, ADC converter - 12 d B to +48 d B low noise Rx PGA (<3 n V/√Hz) Third-order, programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Pin patible with the AD9865 Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in a 64-lead LFCSP_VQ FUNCTIONAL BLOCK DIAGRAM IOUTP+ IOUTP- PWRDWN MODE TXEN/TXSYNC TXCLK/TXQUIET ADIO[9:4]/ Tx[5:0] 10 2-4X Tx DAC 0 TO - 7.5d B IAMP 0 TO - 12d B IOUTN+ IOUTN- CLK SYNC. 2M CLK MULTIPLIER CLKOUT1 CLKOUT2 OSCIN XTAL ADIO[3:0]/ Rx[5:0] 10 RXEN/RXSYNC RXCLK AGC[5:0] PORT SPI PORT 6 06733-001 ADC 80MSPS 0 TO 6d B 2-POLE LPF RX+ 1-POLE LPF APPLICATIONS Broadband wireline networking RX- REGISTER Δ = 1d B CONTROL - 6 TO +18d B - 6 TO +24d B Δ = 6d B Δ = 6d B Figure 1. .. GENERAL DESCRIPTION The AD9868 is a mixed-signal front-end (Mx FE®) IC for transceiver applications requiring Tx path and Rx path functionality with data rates up to 80 MSPS. A lower cost, pinpatible version of the AD9865, the AD9868 removes the current amplifier (IAMP) IOUTP functionality and limits the PLL VCO operating range of 80 MHz to 200 MHz. The part is well-suited for half- and full-duplex applications. The digital interface is extremely flexible, allowing simple interfacing to digital back ends that support half- or full-duplex data transfers, often allowing the AD9868 to replace discrete ADC and DAC solutions. Power-saving modes include the ability to reduce power consumption of individual functional blocks or power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two...