ADATE207 Datasheet | Analog Devices

FEATURES 4-channel timing formatter 256 waveforms per channel 4 independent event edges per waveform STIL IEEE 1450-1999-patible events 4-period range for each edge 39.06 ps timing resolution 2.5 ns minimum edge refire rate All drive formats supported 100 MHz base vector rate ×2 and ×4 high speed modes ×2 pin multiplexing 1 ns minimum pulse width 32-bit fail counter per channel 4-bit pin capture per channel Air cooled, low power CMOS design 6 W at 100 MHz base rate 2.5 V power supply Differential DCL interface control TMU multiplexer .. FUNCTIONAL BLOCK DIAGRAM PATTERN TIME SET MEMORY QUAD EDGE GENERATOR FAIL DETECTION FORMAT PARE LOGIC DCL INTERFACE FAIL PATTERN TIME SET MEMORY QUAD EDGE GENERATOR FAIL DETECTION FAIL FORMAT PARE LOGIC DCL INTERFACE PATTERN TIME SET MEMORY QUAD EDGE GENERATOR FAIL DETECTION FAIL FORMAT PARE LOGIC DCL INTERFACE PATTERN TIME SET MEMORY QUAD EDGE GENERATOR FAIL DETECTION Automatic test equipment (ATE) High speed digital instrumentation Pulse generation Figure 1. GENERAL DESCRIPTION The ADATE207 is a timing generator and formatter for automatic test equipment (ATE) equipment. The ADATE207 provides four independent channels with a 100 MHz base vector rate of timing and formatting for ATE digital pins. It interfaces between the pattern memory,and the driver, parator, and load (DCL) chips for plete digital pins. The ADATE207 accepts up to eight bits of pattern data per pin and can produce formatted outputs and perform parisons of DUT expected responses. Each channel of the ADATE207 provides 256 selectable waveforms, wherein each waveform consists of up to four possible events. Each event consists of a programmable timing edge and a STIL-patible (IEEE Standard 1450-1999) set. Each timing edge generator can produce an edge with a span of four periods with a 39.06 ps edge placement resolution. The delay generators use a reference master clock of 100 MHz and provide programmable delays based upon counts of the...