ADN4666 Datasheet | Analog Devices

FEATURES ±8 k V ESD IEC 61000-4-2 contact discharge on receiver input pins 400 Mbps (200 MHz) switching rates 100 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 3.3 ns propagation delay (maximum) 3.3 V power supply High impedance outputs on power-down Low power design (10 m W quiescent typical) Interoperable with existing 5 V LVDS drivers Accepts small swing (350 m V typical) differential input signal levels Supports open, short, and terminated input fail-safe Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range of - 40°C to +85°C Available in surface-mount SOIC package and low profile TSSOP package ROUT2 R2 RIN2+ RIN2- GND R3 ROUT3 RIN3+ 08097-001 RIN3- Figure 1. APPLICATIONS Point-to-point data transmission Multidrop buses Clock distribution networks Backplane receivers GENERAL DESCRIPTION The ADN4666 is a quad-channel, CMOS low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. The device accepts low voltage (350 m V typical) differential input signals and converts them to a single-ended, 3 V TTL/CMOS logic level. The ADN4666 also offers active high and active low enable/disable inputs (EN and EN) that control all four receivers. These inputs disable the receivers and switch the outputs to a high impedance state. Consequently, the outputs of one or more ADN4666 devices can be multiplexed together to reduce the quiescent power consumption to 10 m W typical. The ADN4666 and its panion driver, the ADN4665, offer a new solution to high speed, point-to-point data transmission and offer a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use....