Click to expand full text
SUMMARY
High performance 32-Bit DSP—applications in audio, medical, military, wireless communications, graphics, imaging, motor-control, and telephony
Super Harvard Architecture—four independent buses for dual data fetch, instruction fetch, and nonintrusive zerooverhead I/O
Code compatible with all other sharc family DSPs Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Serial ports offer I2S support via 8 programmable and simultaneous receive or transmit pins, which support up to 16 transmit or 16 receive channels of audio
SHARC Processor
ADSP-21161N
Integrated peripherals—integrated I/O processor, 1M bit onchip dual-ported SRAM, SDRAM controller, glueless multipr
ADSP-21161N Datasheet
