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ADSP-21571 - SHARC+ Dual-Core DSP

This page provides the datasheet information for the ADSP-21571, a member of the ADSP-SC570 SHARC+ Dual-Core DSP family.

Description

3 ARM Cortex-A5 Processor 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security

Features

  • Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed ARM Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory pr.

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Datasheet preview – ADSP-21571

Datasheet Details

Part number ADSP-21571
Manufacturer Analog Devices
File Size 3.75 MB
Description SHARC+ Dual-Core DSP
Datasheet download datasheet ADSP-21571 Datasheet
Additional preview pages of the ADSP-21571 datasheet.

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Full PDF Text Transcription

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SHARC+ Dual-Core DSP with ARM Cortex-A5 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SYSTEM FEATURES Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed ARM Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range MEMORY Large on-chip L2 SRAM with ECC
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