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ADSP-21593 - SHARC+ Dual-Core DSP

Description

3 ARM Cortex-A5 Processor (ADSP-SC592/SC594 Only) 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security

Features

  • Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, short word, word, and long word addressability Arm Cortex-A5 core Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16 32 kB L1 instruction and data caches with parity 256 kB L2 cache with parity Powerful DMA system with 8 MemDMAs On-chip.

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Datasheet preview – ADSP-21593

Datasheet Details

Part number ADSP-21593
Manufacturer Analog Devices
File Size 4.38 MB
Description SHARC+ Dual-Core DSP
Datasheet download datasheet ADSP-21593 Datasheet
Additional preview pages of the ADSP-21593 datasheet.

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Full PDF Text Transcription

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SHARC+ Dual-Core DSP with Arm Cortex-A5 ADSP-21593/21594/ADSP-SC592/SC594 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, short word, word, and long word addressability Arm Cortex-A5 core Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16 32 kB L1 instruction and data caches with parity 256 kB L2 cache with parity Powerful DMA system with 8 MemDMAs On-chip memory protection Integrated safety features 17 mm × 17 mm, 400-ball BGA_ED (0.
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