Download the ADSP-2185L datasheet PDF.
This datasheet also covers the ADSP-2184L variant, as both devices belong to the same dsp microcomputer family and are provided as variant models within a single manufacturer datasheet.
Key Features
Up to 19 ns instruction cycle time, 52 MIPS sustained performance
Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every
instruction cycle Multifunction instructions Power-down mode featuring low CMOS standby power dissi-
pation with 400 CLKIN cycle recovery from power-down condition Low power dissipation in idle mode.
Full PDF Text Transcription for ADSP-2185L (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
ADSP-2185L. For precise diagrams, and layout, please refer to the original PDF.
DSP Microcomputer ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PERFORMANCE FEATURES Up to 19 ns instruction cycle time, 52 MIPS sustained performance Single-cycle instruct...
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uction cycle time, 52 MIPS sustained performance Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle Multifunction instructions Power-down mode featuring low CMOS standby power dissi- pation with 400 CLKIN cycle recovery from power-down condition Low power dissipation in idle mode INTEGRATION FEATURES ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions Up to 160K bytes of on-chip RAM, configured Up to 32K words program memory RAM Up to 32K words data memory RAM Dual-purpose program memory for bo
ADSP-2185L Datasheet
