ADSP-2191M - DSP Microcomputer

Features

• 6.25 ns Instruction Cycle Time, for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax Single-Cycle Instruction Execution Single-Cycle Context Switch between Two Sets of Com- putation and Memory Instructions Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Pipelined Architecture Supports Efficient Code Execution Architectural Enhancements for Compiled C and C++ Code Efficiency Archit.