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ADSP-2192M - DSP Microcomputer

Description

3 DSP Core Architecture

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Features

  • 320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package with PCI, USB, Sub-ISA, and CardBus Interfaces 3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface with Bus Mastering over Four DMA Channels with Scatter-Gather Support Integrated USB 1.1 Compliant Interface Sub-ISA Interface AC’97 Revision 2.1 Compliant Interface for External Audio, Modem, and Handset Codecs with DMA Capability Dual ADSP-219x Core Processors (P0 and P1) on Each ADSP-2192M DSP Chip 132K Words of Memory Includes 4K ؋ 16-Bit Shar.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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m o .c U 4 t e e h S a at .D w w w a DSP Microcomputer ADSP-2192M 80K Words of On-Chip RAM on P0, Configured as 64K Words On-Chip 16-Bit RAM for Data Memory and 16K Words On-Chip 24-Bit RAM for Program Memory 48K Words of On-Chip RAM on P1, Configured as 32K Words On-Chip 16-Bit RAM for Data Memory and 16K Words On-Chip 24-Bit RAM for Program Memory 4K Words of Additional On-Chip RAM Shared by Both Cores, Configured as 4K Words On-Chip 16-Bit RAM Flexible Power Management with Selectable PowerDown and Idle Modes Programmable PLL Supports Frequency Multiplication, Enabling Full Speed Operation from Low Speed Input Clocks 2.5 V Internal Operation Supports 3.3 V/5.
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