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ADSP21msp59 - (ADSP21msp58 / ADSP21msp59) DSP Microcomputers

This page provides the datasheet information for the ADSP21msp59, a member of the ADSP-21msp58 (ADSP21msp58 / ADSP21msp59) DSP Microcomputers family.

Description

The ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Processors (MSProcessor® DSPs) are fully integrated, single-chip DSPs complete with a high performance analog front end.

Features

  • 38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz Crystal ADSP-2100 Family Code and Function Compatible with New Instruction Set Enhanced for Bit Manipulation Instructions, Multiplication Instructions, Biased Rounding, and Global Interrupt Masking 2K ؋ 24 Words of On-Chip Program Memory RAM 2K ؋ 16 Words of On-Chip Data Memory RAM 4K ؋ 24 Words of On-Chip Program Memory ROM (ADSP-21msp59 Only) 8-Bit Parallel Host Interface Port Analog Interface Provides: 16-Bit Sigma-Delta ADC and DAC Progra.

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Datasheet preview – ADSP21msp59

Datasheet Details

Part number ADSP21msp59
Manufacturer Analog Devices
File Size 372.56 KB
Description (ADSP21msp58 / ADSP21msp59) DSP Microcomputers
Datasheet download datasheet ADSP21msp59 Datasheet
Additional preview pages of the ADSP21msp59 datasheet.

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Full PDF Text Transcription

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a FEATURES 38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz Crystal ADSP-2100 Family Code and Function Compatible with New Instruction Set Enhanced for Bit Manipulation Instructions, Multiplication Instructions, Biased Rounding, and Global Interrupt Masking 2K ؋ 24 Words of On-Chip Program Memory RAM 2K ؋ 16 Words of On-Chip Data Memory RAM 4K ؋ 24 Words of On-Chip Program Memory ROM (ADSP-21msp59 Only) 8-Bit Parallel Host Interface Port Analog Interface Provides: 16-Bit Sigma-Delta ADC and DAC Programmable Gain Stages On-Chip Anti-Aliasing & Anti-Imaging Filters 8 kHz Sampling Frequency 65 dB ADC, SNR and THD 72 dB DAC, SNR and THD 425 mW Typical Power Dissipation @ 5.
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