AS4SD4M16 Datasheet | Austin Semiconductor

FEATURES - - - - - - - - - - - - - .. PIN ASSIGNMENT (Top View) 54-Pin TSOP Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C WRITE Recovery ( t WR/ t DPL) t WR = 2 CLK Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge and Auto Refresh Modes Self Refresh Mode (Industrial, -40°C to 85° C only) 4,096-cycle refresh LVTTL-patible inputs and outputs Single +3.3V ±0.3V power supply Longer lead TSOP for improved reliability (OCPL- ) Short Flow / Long Flow Test Screening Options OPTIONS - - MARKING 4M16 No. 901 Note: “” indicates an active low. Configurations 4 Meg x 16 (1 Meg x 16 x 4 banks) Plastic Package - OCPL- 54-pin TSOP (400 mil) DG Timing (Cycle Time) 8ns; t AC = 6.5ns @ CL = 3 ( t RP - 24ns) 10ns; t AC = 9ns @ CL = 2 Operating Temperature Ranges -Military (-55°C to +125° C) -Industrial Temp (-40°C to 85° C) - -8 -10 - XT IT 4 Meg x 16 Configuration 1 Meg x 16 x 4 banks Refresh Count 4K Row Addressing 4K (A0-A11) Bank Addressing 4 (BA0, BA1) Column Addressing 256 (A0-A7) KEY TIMING PARAMETERS SPEED GRADE -8 -10 -8 -10 CLOCK ACCESS TIME FREQUENCY CL = 2- - CL = 3- - 125 MHz - 6.5ns 100 MHz - 7ns 83 MHz 9ns - 66 MHz 9ns - SETUP TIME 2ns 3ns 2ns 3ns HOLD TIME 1ns 1ns 1ns 1ns - Off-center parting line - - CL = CAS (READ) latency For more products and information please visit our web site at .austinsemiconductor. AS4SD4M16 Rev. 1.5 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SDRAM Austin Semiconductor, Inc. GENERAL DESCRIPTION The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock...