CY27C128 Datasheet | Cypress

Wide speed range Ċ 45 ns to 200 ns (mercial and military) D Low power Ċ 248 m W (mercial) Ċ 303 m W (military) D Low standby power Ċ Less than 83 m W when deselected D ±10% Power supply tolerance .. Features Functional Description The CY27C128 is a highĆperformance 16,384Ćword by 8Ćbit CMOS EPROM. When disabled (CE HIGH), the Logic Block Diagram A 13 A 12 A 11 A 10 A9 ROW ADDRESS 128 x 1024 PROGRAMABLE ARRAY CY27C128 automatically powers down into a lowĆpower standĆby mode. The CY27C128 is packaged in the industry standard 600Ćmil DIP and LCC packages. The CY27C128 is also available in a CerĆ DIP package equipped with an erasure window to provide for reprogrammability. When exposed to UV light, the EPROM is erased and can be reprogrammed. The memory cells utilize proven EPROM floating gate technology and byteĆwide inĆ telligent programming algorithms. The CY27C128 offers the advantage of lower power and superior performance and programming yield. The EPROM cell reĆ quires only 12.5V for the super voltage, 128K (16K x 8ĆBit) CMOS EPROM CY27C128 and low current requirements allow for gang programming. The EPROM cells alĆ low each memory location to be tested 100% because each location is written into, erased, and repeatedly exercised prior to encapsulation. Each EPROM is also tested for AC performance to guarĆ antee that after customer programming, the product will meet both DC and AC specification limits. Reading the CY27C128 is acplished by placing active LOW signals on OE and CE . The contents of the memory location addressed by the address lines (A 0 - A 13 ) will bee available on the output lines (O 0 - O 7 ). Pin Configurations O7 DIP/Flatpack 8 x 1 OF 128 MULTIPLEXER O6 V PP A 12 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27C128 23 22 21 20 19 18 17 16 15 28 27 26 25 24 V CC PGM A 13 A8 A9 A 11 OE A 10 CE O7 O6 O5 O4 O3 A6 A5 A4 A3 A2 A1 A0 NC O0 5 6 7 8 9 10 11 12 13 LCC/PLCC [1] PGM CC PP 12 DU 7 A A 4 A V V 13 1 32 31...