Datasheet4U Logo Datasheet4U.com

CY28347 - Universal Single-chip Clock Solution

General Description

Description Oscillator Buffer Input.

Connect to a crystal or to an external clock.

Oscillator Buffer Output.

Key Features

  • Supports VIA P4M266/KM266 chipsets Supports Pentium® 4, Athlon processors Supports two DDR DIMMS Provides.
  • Two different programmable CPU clock pairs.
  • Six differential DDR SDRAM pairs.
  • Two low-skew/low-jitter AGP clocks.
  • Six low-skew/low-jitter PCI clocks.
  • One 48M output for USB.
  • One programmable 24M or 48M for SIO.
  • Dial-a-Frequency and Dial-a-dB features.
  • Spread Spectrum for best e.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY28341 Universal Single-Chip Clock Solution SpectraLinear
CY28346-2 Clock Synthesizer Silicon Laboratories
CY28349 FTG SpectraLinear
CY28322-2 133 Mhz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Cypress
CY28354-400 210MHz 24 Output Buffer Silicon Laboratories

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY28341 Universal Single-Chip Clock Solution
CY28342 High-performance SiS645/650 Pentium 4 Clock Synthesizer
CY28343 Zero Delay SDR/DDR Clock Buffer
CY28344 FTG
CY28346 Clock Synthesizer with Differential CPU Outputs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY28347 Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems Features • • • • Supports VIA P4M266/KM266 chipsets Supports Pentium® 4, Athlon processors Supports two DDR DIMMS Provides — Two different programmable CPU clock pairs — Six differential DDR SDRAM pairs — Two low-skew/low-jitter AGP clocks — Six low-skew/low-jitter PCI clocks — One 48M output for USB — One programmable 24M or 48M for SIO • Dial-a-Frequency and Dial-a-dB features • Spread Spectrum for best electromagnetic interference (EMI) reduction • SMBus-compatible for programmability • 56-pin SSOP and TSSOP packages Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU 66.80 100.20 120.00 133.33 72.00 105.00 160.00 140.00 77.00 110.