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CY2PP3210 - Dual 1:5 Differential Clock / Data Fanout Buffer

Datasheet Summary

Description

The CY2PP3210 is a low-skew, low propagation delay dual 1-to-5 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications.

Features

  • Dual sets of five ECL/PECL differential outputs.
  • Two ECL/PECL differential inputs.
  • Hot-swappable/-insertable.
  • 50 ps output-to-output skew.
  • 150 ps device-to-device skew.
  • 500 ps propagation delay (typical).
  • 0.8 ps RMS period jitter (max. ).
  • 1.5 GHz Operation (2.2 GHz max. toggle frequency).
  • PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V.
  • ECL mode supply range: VE E =.
  • 2.5V± 5% to.

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Datasheet Details

Part number CY2PP3210
Manufacturer Cypress Semiconductor
File Size 300.95 KB
Description Dual 1:5 Differential Clock / Data Fanout Buffer
Datasheet download datasheet CY2PP3210 Datasheet
Additional preview pages of the CY2PP3210 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com FastEdge™ Series CY2PP3210 Dual 1:5 Differential Clock/Data Fanout Buffer Features • Dual sets of five ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50 ps output-to-output skew • 150 ps device-to-device skew • 500 ps propagation delay (typical) • 0.8 ps RMS period jitter (max.) • 1.5 GHz Operation (2.2 GHz max. toggle frequency) • PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V • Industrial temperature range: –40°C to 85°C • 32-pin 1.
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