CY62148V Datasheet | Cypress

Mo BL CY62148V Mo BL™ 512K x 8 Mo BL Static RAM Features - Low voltage range: - 2.7V- 3.6V - Ultra low active power - Low standby power - TTL-patible inputs and outputs - Automatic power-down when deselected - CMOS for optimum speed/power The device can be put into standby mode when deselected (CE HIGH). Writing to the device is acplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is acplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII, and a 32-pin SOIC package. Functional Description The CY62148V is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. This device Features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (Mo BL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. Logic Block Diagram Data in Drivers I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 512K x 8 ARRAY CE WE COLUMN DECODER POWER DOWN I/O6 I/O7 A10 A11 A12 A13 A14 A15 A16 A17 A18 62148V-1 Cypress Semiconductor Corporation - 3901 North First Street - San...