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CY7C1041BV33 - 256K x 16 Static RAM

Download the CY7C1041BV33 datasheet PDF (CY7 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 256k x 16 static ram.

Description

of read and write modes.

The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

Features

  • High speed.
  • tAA = 12 ns.
  • Low active power.
  • 612 mW (max. ).
  • Low CMOS standby power (Commercial L version).
  • 1.8 mW (max. ).
  • 2.0V Data Retention (600 µW at 2.0V retention).
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE and OE features written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C1041B.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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041BV33 CY7C1041BV33 256K x 16 Static RAM Features • High speed — tAA = 12 ns • Low active power — 612 mW (max.) • Low CMOS standby power (Commercial L version) — 1.8 mW (max.) • 2.0V Data Retention (600 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
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