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CY7C1041BV33 - 256K x 16 Static RAM

Download the CY7C1041BV33 datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 256k x 16 static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

of read and write modes.

The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

Key Features

  • High speed.
  • tAA = 12 ns.
  • Low active power.
  • 612 mW (max. ).
  • Low CMOS standby power (Commercial L version).
  • 1.8 mW (max. ).
  • 2.0V Data Retention (600 µW at 2.0V retention).
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE and OE features written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C1041B.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GE 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GN 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1049GN 4-Mbit (512K words x 8 bit) Static RAM Cypress
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1041B 256K x 16 Static RAM
CY7C1041BN 256K x 16 Static RAM
CY7C1041 256K x 16 Static RAM
CY7C1041CV33 256K x 16 Static RAM
CY7C1041D 4-Mbit (256K x 16) Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
041BV33 CY7C1041BV33 256K x 16 Static RAM Features • High speed — tAA = 12 ns • Low active power — 612 mW (max.) • Low CMOS standby power (Commercial L version) — 1.8 mW (max.) • 2.0V Data Retention (600 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH.