Datasheet4U Logo Datasheet4U.com

CY7C1041CV33 - 256K x 16 Static RAM

This page provides the datasheet information for the CY7C1041CV33, a member of the CY7 256K x 16 Static RAM family.

Datasheet Summary

Description

of Read and Write modes.

I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW).

Features

  • Pin equivalent to CY7C1041BV33.
  • High speed.
  • tAA = 10 ns.
  • Low active power.
  • 324 mW (max. ).
  • 2.0V data retention.
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE and OE features HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8.
  • I/O15) is written into the location specified on the address pins (A0.
  • A17). Reading from the device is accomplished.

📥 Download Datasheet

Datasheet preview – CY7C1041CV33

Datasheet Details

Part number CY7C1041CV33
Manufacturer Cypress Semiconductor
File Size 226.39 KB
Description 256K x 16 Static RAM
Datasheet download datasheet CY7C1041CV33 Datasheet
Additional preview pages of the CY7C1041CV33 datasheet.

📁 Similar Datasheet

  • CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
  • CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
  • CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
  • CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)
  • CY7C106D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor

Full PDF Text Transcription

Click to expand full text
CY7C1041CV33 256K x 16 Static RAM Features • Pin equivalent to CY7C1041BV33 • High speed — tAA = 10 ns • Low active power — 324 mW (max.) • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15.
Published: |