CY7C1041D Datasheet | Cypress

4-Mbit (256 K × 16) Static RAM Features - Pin-and function-patible with CY7C1041B - High speed - t AA = 10 ns - Low active power - ICC = 90 m A at 10 ns (Industrial) - Low CMOS standby power - ISB2 = 10 m A - 2.0 V data retention - Automatic power-down when deselected - TTL-patible inputs and outputs - Easy memory expansion with CE and OE Features - Available in Pb-free 44-Pin (400-Mil) Molded SOJ and 44-Pin TSOP II packages Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 INPUT BUFFER 256K x 16 ROW DECODER SENSE AMPS Functional Description[1] The CY7C1041D is a high-performance CMOS static RAM organized as 256K words by 16 bits. Writing to the device is acplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is acplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a plete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041D is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. I/O0- I/O7 I/O8- I/O15 COLUMN DECODER A9 A10 A 11 A12 A13 A14 A15 A16...