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CY7C1041D - 4-Mbit (256K x 16) Static RAM

General Description

The CY7C1041D is a high-performance CMOS static RAM organized as 256K words by 16 bits.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW.

Key Features

  • Pin-and function-compatible with CY7C1041B.
  • High speed.
  • tAA = 10 ns.
  • Low active power.
  • ICC = 90 mA at 10 ns (Industrial).
  • Low CMOS standby power.
  • ISB2 = 10 mA.
  • 2.0 V data retention.
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE and OE features.
  • Available in Pb-free 44-Pin (400-Mil) Molded SOJ and 44-Pin TSOP II packages Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 INPUT BUFFE.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1041D 4-Mbit (256 K × 16) Static RAM Features ■ Pin-and function-compatible with CY7C1041B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA at 10 ns (Industrial) ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 44-Pin (400-Mil) Molded SOJ and 44-Pin TSOP II packages Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 INPUT BUFFER 256K x 16 ROW DECODER SENSE AMPS Functional Description[1] The CY7C1041D is a high-performance CMOS static RAM organized as 256K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW.