CY7C1059DV33 Datasheet | Cypress

Features - High speed - t AA = 10 ns - Low active power - ICC = 110 m A at f = 100 MHz - Low CMOS standby power - ISB2 = 20 m A - 2.0 V data retention - Automatic power down when deselected - TTL-patible inputs and outputs - Easy memory expansion with CE and OE Features - Available in Pb-free 44-pin TSOP-II package - Offered in standard and high reliability (Q) grades Logic Block Diagram 8-Mbit (1M × 8) Static RAM Functional Description The CY7C1059DV33 is a high performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input or output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE LOW and WE LOW). The CY7C1059DV33 is available in 44-pin TSOP-II package with center power and ground (revolutionary) pinout. ROW DECODER SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE WE OE INPUT BUFFER 1M x 8 ARRAY COLUMN DECODER POWER DOWN IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 A11 A12 A13 A14 A15 A16 A17 A18 A19 Cypress Semiconductor Corporation - 198 Champion Court Document #: 001-00061 Rev. - H - San Jose, CA...