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CY7C1148KV18 Datasheet 18-mbit Ddr Ii+ Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.

Key Features

  • 18-Mbit density (1M × 18, 512K × 36).
  • 450-MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.0 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
  • Data valid pin (QVLD) to indicate valid data on the output.
  • Syn.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1148V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1141V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1143KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1143V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1145V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1146V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1150V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1156V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture

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