CY7C1276V18 Datasheet 1.8v Synchronous Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1276V18
Manufacturer	Cypress (now Infineon)
File Size	404.82 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1276V18 CY7C1261V18 Datasheet (PDF)

Separate independent read and write data ports.
Supports concurrent transactions.
300 MHz to 400 MHz clock for high bandwidth.
4-Word Burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz.
Read latency of 2.5 clock cycles.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed.

Part Number	Description
CY7C12701KV18	1.8 V synchronous pipelined SRAM
CY7C1270KV18	36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C12771KV18	1.8 V synchronous pipelined SRAM
CY7C1212F	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F	1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F	1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215H	1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1217F	1-Mbit (32K x 36) Flow-Through Sync SRAM