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CY7C1276V18 - 1.8V Synchronous Pipelined SRAM

Download the CY7C1276V18 datasheet PDF. This datasheet also covers the CY7C1261V18 variant, as both devices belong to the same 1.8v synchronous pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 300 MHz to 400 MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz.
  • Read latency of 2.5 clock cycles.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1261V18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CY7C1041GE 4-Mbit (256K words x 16 bit) Static RAM Cypress
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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C12701KV18 1.8 V synchronous pipelined SRAM
CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C12771KV18 1.8 V synchronous pipelined SRAM
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz ■ Read latency of 2.