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CY7C1304DV25 Datasheet 9-mbit Burst Of 4 Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: PRELIMINARY CY7C1304DV25 9-Mbit Burst of 4 Pipelined SRAM with QDR™.

Key Features

  • Separate independent Read and Write data ports.
  • Supports concurrent transactions.
  • 167-MHz Clock for high bandwidth.
  • 2.5 ns Clock-to-Valid access time.
  • 4-Word Burst for reducing the address bus frequency.
  • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) ac.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C130 1K x 8 Dual-Port Static RAM
CY7C1302CV25 9-Mbit Burst of Two Pipelined SRAMs
CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs
CY7C1303BV18 18-Mbit Burst of 2 Pipelined SRAM
CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM
CY7C1305BV18 18-Mbit Burst of 4 Pipelined SRAM
CY7C1305BV25 18-Mbit Burst of 4 Pipelined SRAM
CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM
CY7C1307BV18 18-Mbit Burst of 4 Pipelined SRAM
CY7C1307BV25 18-Mbit Burst of 4 Pipelined SRAM

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