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CY7C1306BV18 - 18-Mbit Burst of 2 Pipelined SRAM

Download the CY7C1306BV18 datasheet PDF (CY7C1303BV18 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 18-mbit burst of 2 pipelined sram.

Description

Separate independent Read and Write data ports Supports concurrent transactions 167-MHz Clock for high bandwidth 2.5 ns Clock-to-Valid access time 2-Word Burst on all accesses Double Data Rate (DDR) interfaces on both Read and Write Ports

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1303BV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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CY7C1303BV18 CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 1.
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